1. Field of the Invention
The subject invention relates generally to data communication techniques and particularly to data communication between a processing unit and a memory device.
2. Description of the Related Art
Modern computer systems typically comprise a processing unit and a memory device. The processing unit executes programs, provides computations, etc., as is well known to those skilled in the art. Due to various restraints, the processing unit usually has a limited amount of “on-board” memory to store data. Therefore, external memory is commonly utilized to store the data not stored on the processing unit itself.
One constraint of such computer systems is the speed at which data may be transferred between the processing unit and the memory device. At high speeds, synchronization of a clock signal produced by processing unit and data signals flowing between the processing unit and the memory device must be precisely coordinated. More exactly, when the computer system utilizes synchronous clocking, an alignment between the clock signal and the data signal that allows latching of the data with sufficient margin is necessary.
The clock signal and the data signal must be transmitted and/or received with a well-defined offset in order to ensure such an alignment. For example, in a double-data rate (“DDR”) implementation, an offset of 90 degrees between the clock signal and the data signal is typically utilized, while in a single-data rate (“SDR”) implementation, an offset of 180 degrees is typically utilized.
In the prior art, a circuit such as a delay-locked loop (“DLL”) is often utilized to establish the well-defined offset. However, such circuits require a large physical area, consume precious power resources, and have relatively long locking times in order to function. These long lock times often restrict some features of the system, such as fast and/or frequent power-down cycles.
Another prior art implementation requires utilizing clocks having a higher speed than the data rate; using both the rising and falling edges of the clock signal to establish the phase offset. For example, if the DDR data speed is 1 billion bits per second (“gbps”), a clock of 1 GHz could be utilized where the rising edge of the “clocks”, i.e., regulate, the data signal and the falling edge clocks another signal such as a strobe with a half unit interval shift. However, such an implementation may produce physical limitations in the silicon that restricts the top speed of the clock signal.
Accordingly, a data communication system and method utilizing less physical area and less power is desirable. A data communications system with shorter locking times is also desirable. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.